Musical Christmas Tree

Technical Details

Basic Starter Set
The current Musical Christmas Tree is based on an ISA card. This is old technology, so it will be described briefly. The ISA card has been extended by means of a shift register to accomodate more channels. This will be described in more detail, inasmuch as it has the potential of being used with a standard parallel port, thus extending the useful life of the technology.

The ISA card consists of fairly standard logic chips. The address is sensed by a 74LS688 "totem pole" comparator. When the address on the bus matches the pattern wired to the chip, the card select line (pin 19) is pulled low. The bit pattern is compared to
bits A[11:4] on the address bus.
The card select line and IOW line together trigger a
74LS154 4-to-16 decoder that senses address
bits A[3:0] and pulls one of Chip Select 0 through 15 low appropriately.
The data flow is controlled by a 74LS245 transceiver. The eight data bits are simultaneously sent to all 16 octal flipflips, at most one of which will be active at any given time.
Each Chip Select line controls a single 74LS273 octal flipflop (alias "shift register" as we shall see in a moment). There are 16 of these for a total of 128 bits.
Each of the output bits from the flipflops triggers a transistor, which in turn triggers an optoisolator on the "back end" of the control box. The output from the optoisolator triggers a triac in the standard way, and the 110-volt current is switched on or off appropriately. A separate (old PC) power supply is used on the "back end" to isolate the 110 Volt switching from the motherboard.

Extending Beyond 16 Bytes
In order to extend the card to accommodate more than 128 circuits, one of two methods can be used.
"Brute force" would somehow extend the on-card addressing to five bits instead of four, and some kind of 5-to-32 decoder would have to be cobbled together as I am unaware of any such chip.
Alternatively, the address circuitry could be duplicated to sense a different address. Either of these alternatives would require "fixing" something that already works and has been alive and well for nearly ten years.
The third alternative is to build a shift register. This is what I chose.

I chose to build it in a "parallel" fashion starting with the last '273 (number 15) on the present card. This chip becomes the first in a chain of identical chips all activated by the same Chip Select 15 line that goes to the CLK ("clock") pin of the '273. The CLK pin is the common Enable line for all of the flipflops on each chip. Edge-triggering transfers the input bits to the output bits at different times (falling and rising edges of the CLK signal that is active low). The eight output bits of each chip in the chain go to the appropriate output transistor, and, in addition, to the eight input bits of the next chip. The software sends as many appropriate bytes to that same address as there are flipflops in the register. The byte moves from chip to chip with each CLK signal (hence the name "shift" register).

There is one complication. Although the bits in transit only change the transistor outputs for less than a microsecond, triacs do not respond in like manner. If the transient signal were to be sent to the incandescent light bulbs for so brief a time, there would be no perceptible changes; however, triacs, although they can be turned on at any time, turn off only when the zero-crossing of the AC current occurs. This means that we could see a spurious flash of some lights up to 10 milliseconds in duration, which might actually become visible as faint blinks to the annoyance of the audience.

Note: I had to run the display without using the '244s and stuff flickered like crazy. Didn't bother the audience much but it annoyed the fire out of me! We just pretended that it was part of the show while I worked out the "fanout" outlined below. It might be corrected with some fancy assembly language but I understand the hardware solution a lot better.

It would seem that if the entire display were switched off for mere microseconds that it would be less distracting by far, to the point of being undetectable since filaments do not cool off that fast. If a string of lights is 0.000001 second late in switching on, no one will notice. Therefore, we use another set of chips in parallel with the flipflops.

The 74LS244 octal buffer is a good choice. Standing between the output of the flipflop and the transistors, it switches all the transistors off when bytes are in transit through the register, and then back to the state of the flipflop when the shifting stops. 99% of the time there will be no actual change in the state of the triac, since switching off and on has no effect at all unless the current is at a zero crossing.
Admittedly, the placement of inputs and outputs on both the '273 and the '244 are annoying; I drew very careful diagrams on graph paper showing the placement and wiring of the pins viewed from the underside of the board. This probably saved endless hours of grief while wire-wrapping all of the connections. The '244 is divided into two sets of four buffers; hence there are two CLK1 connections as shown in the diagram. CLK1 is different from CLK; it will be explained shortly.
Diagram shows only connection to '244. Connection to next '273 in the shift register is not shown here.

The big trick is to keep the '244s off during the entire shift. To this end, a divide-by-four (or eight, or sixteen) counter may be used. 74LS107 dual JK flipflops are used. Two flipflops (one chip) yields a divide-by-four; each additional JK flipflop divides by a successively higher power of 2. Output from each of the flipflops goes to the CLK of the next flipflop (inputs both held high at all times), and also to a multiple-input OR gate that is simply constructed from an appropriate number of diodes and a pulldown resistor. Output from this gate is CLK1.

The CLK (Chip Select 15) signal and outputs from all of the JK flipflops are thus combined. Only when all of these signals are low will the '244 transmit data, since its control lines are active low. When the control lines are high, the outputs float. However, since the transistors require a definite high to fire, this is effectively the same as all outputs going low. Therefore, pulldown resistors are not required. (Hey, it works! Don't mess with success!)

Parallel Port
I have not built any of what follows, but here are my thoughts on the design:

The parallel port has eight output bits and three control lines. Two of the control lines are active low and one is active high.
The eight output bits obviously go to the inputs of the first '273.
Each succeeding '273 is daisy-chained as described above.
The CLK signal (active low) is one of the control lines from the port. It goes to every '273.
The CLK signal also goes to the first JK flipflop in the frequency divider.
The CLK signal is combined with outputs from all JK flipflops via a multiple-input OR gate that may be constructed as described above.
The output of the OR gate controls the '244 buffers.
That's it! Eight data bits and one control line, and an unlimited number of output channels, all done by the magic of a shift register.

One word of warning: too many devices hanging off the single control line will be too much of a load. About every eighth flipflop, some kind of amplification must be provided. Two inverter gates in succession (logical NOT-NOT, no change) on a 7404 will in turn power eight or ten more gates; however, timings are important and I would recommend using some sort of buffer or line driver chip for signal amplification. The smaller response time, the better. I will be trying the 74LS125, using a fanout of 8 (2 to each of 4 '244s).

The ISA card consists of fairly standard logic chips. The address is sensed by a `74LS688` "totem pole" comparator. When the address on the bus matches the pattern wired to the chip, the `card select` line (pin 19) is pulled `low`. The bit pattern is compared to bits `A[11:4]` on the address bus.
The `card select` line and `IOW` line together trigger a `74LS154` 4-to-16 decoder that senses address bits `A[3:0]` and pulls one of `Chip Select 0` through `15 low` appropriately.
The data flow is controlled by a `74LS245` transceiver. The eight data bits are simultaneously sent to all 16 octal flipflips, at most one of which will be active at any given time.
Each `Chip Select` line controls a single `74LS273` octal flipflop (alias "shift register" as we shall see in a moment). There are 16 of these for a total of 128 bits.
Each of the output bits from the flipflops triggers a transistor, which in turn triggers an optoisolator on the "back end" of the control box. The output from the optoisolator triggers a triac in the standard way, and the 110-volt current is switched on or off appropriately. A separate (old PC) power supply is used on the "back end" to isolate the 110 Volt switching from the motherboard.
Extending Beyond 16 Bytes In order to extend the card to accommodate more than 128 circuits, one of two methods can be used. "Brute force" would somehow extend the on-card addressing to five bits instead of four, and some kind of 5-to-32 decoder would have to be cobbled together as I am unaware of any such chip. Alternatively, the address circuitry could be duplicated to sense a different address. Either of these alternatives would require "fixing" something that already works and has been alive and well for nearly ten years. The third alternative is to build a shift register. This is what I chose.
I chose to build it in a "parallel" fashion starting with the last `'273` (number 15) on the present card. This chip becomes the first in a chain of identical chips all activated by the same `Chip Select 15` line that goes to the `CLK` ("clock") pin of the `'273`. The `CLK` pin is the common `Enable` line for all of the flipflops on each chip. Edge-triggering transfers the input bits to the output bits at different times (falling and rising edges of the `CLK` signal that is active `low`). The eight output bits of each chip in the chain go to the appropriate output transistor, and, in addition, to the eight input bits of the next chip. The software sends as many appropriate bytes to that same address as there are flipflops in the register. The byte moves from chip to chip with each `CLK` signal (hence the name "shift" register).


There is one complication. Although the bits in transit only change the transistor outputs for less than a microsecond, triacs do not respond in like manner. If the transient signal were to be sent to the incandescent light bulbs for so brief a time, there would be no perceptible changes; however, triacs, although they can be turned on at any time, turn off only when the zero-crossing of the AC current occurs. This means that we could see a spurious flash of some lights up to 10 milliseconds in duration, which might actually become visible as faint blinks to the annoyance of the audience. Note: I had to run the display without using the `'244`s and stuff flickered like crazy. Didn't bother the audience much but it annoyed the fire out of me! We just pretended that it was part of the show while I worked out the "fanout" outlined below. It might be corrected with some fancy assembly language but I understand the hardware solution a lot better. It would seem that if the entire display were switched off for mere microseconds that it would be less distracting by far, to the point of being undetectable since filaments do not cool off that fast. If a string of lights is 0.000001 second late in switching on, no one will notice. Therefore, we use another set of chips in parallel with the flipflops.



The 74LS244 octal buffer is a good choice. Standing between the output of the flipflop and the transistors, it switches all the transistors off when bytes are in transit through the register, and then back to the state of the flipflop when the shifting stops. 99% of the time there will be no actual change in the state of the triac, since switching off and on has no effect at all unless the current is at a zero crossing.
Admittedly, the placement of inputs and outputs on both the `'273` and the `'244` are annoying; I drew very careful diagrams on graph paper showing the placement and wiring of the pins viewed from the underside of the board. This probably saved endless hours of grief while wire-wrapping all of the connections. The `'244` is divided into two sets of four buffers; hence there are two CLK1 connections as shown in the diagram. CLK1 is different from CLK; it will be explained shortly.	Diagram shows only connection to '244. Connection to next '273 in the shift register is not shown here.
The big trick is to keep the `'244`s off during the entire shift. To this end, a divide-by-four (or eight, or sixteen) counter may be used. `74LS107` dual JK flipflops are used. Two flipflops (one chip) yields a divide-by-four; each additional JK flipflop divides by a successively higher power of 2. Output from each of the flipflops goes to the `CLK` of the next flipflop (inputs both held `high` at all times), and also to a multiple-input `OR` gate that is simply constructed from an appropriate number of diodes and a pulldown resistor. Output from this gate is CLK1. The `CLK` (`Chip Select 15`) signal and outputs from all of the JK flipflops are thus combined. Only when all of these signals are `low` will the `'244` transmit data, since its control lines are active `low`. When the control lines are `high`, the outputs float. However, since the transistors require a definite high to fire, this is effectively the same as all outputs going `low`. Therefore, pulldown resistors are not required. (Hey, it works! Don't mess with success!) Parallel Port I have not built any of what follows, but here are my thoughts on the design: The parallel port has eight output bits and three control lines. Two of the control lines are active `low` and one is active `high`. The eight output bits obviously go to the inputs of the first `'273`. Each succeeding `'273` is daisy-chained as described above. The `CLK` signal (active `low`) is one of the control lines from the port. It goes to every `'273`. The `CLK` signal also goes to the first JK flipflop in the frequency divider. The `CLK` signal is combined with outputs from all JK flipflops via a multiple-input `OR` gate that may be constructed as described above. The output of the `OR` gate controls the `'244` buffers. That's it! Eight data bits and one control line, and an unlimited number of output channels, all done by the magic of a shift register. One word of warning: too many devices hanging off the single control line will be too much of a load. About every eighth flipflop, some kind of amplification must be provided. Two inverter gates in succession (logical NOT-NOT, no change) on a 7404 will in turn power eight or ten more gates; however, timings are important and I would recommend using some sort of buffer or line driver chip for signal amplification. The smaller response time, the better. I will be trying the `74LS125`, using a fanout of 8 (2 to each of 4 '244s).